Physical Design on TSMC’s 16nm FinFET for SDN




Client Scenario

The client is a leading industry player in complex ASIC solutions. They had a requirement to enable SDN (Software Defined Network) functionality for a chip that would be used in high-speed computing, networking and storage applications. Given the size and logical complexities, the client had opted for 16nm technology node.


Project Highlights

eInfochips provided a team of expert Physical Design/Implementation engineers to address the most complex of logic blocks for the chip, to achieve Netlist to GDSII signoff.


  • 12 Metal Layer Design for TSMC Tape-out
  • 16nm TSMC FinFET with 3 VT class cells
  • 120+ Logic Blocks with ~5M Gates each across 3 Chip Variants
  • 6500+ Hard Macros integrated
  • Sign-off STA across 12 timing scenarios with Crosstalk and OCV analysis
  • Timing Closure for up to 8 clock domains per block, functional clock at 1 GHz